1. Field of Invention
The invention relates to a method of performing a sequence of semiconductor patterning operations on a substrate and specifically to perform patterning of a structure on the substrate under 10 nm.
2. Description of Related Art
In semiconductor manufacturing patterning of a film on a substrate can be achieved through several methods that have evolved with time to follow Moore's law. The first method is conventional lithography which can no longer be used alone to achieve advanced nodes critical dimensions (CD).
Double patterning is the technique used to create hard mask features smaller than photolithographic capabilities by using spacer deposition to define feature dimensions. Typical double patterning (DP) techniques require a sequence of deposition over a mandrel, etch to form the spacer and another etch to remove the mandrel, with both deposition and etch tools required. There are some spatial limitations inherent in the conventional DP technique due to deposition ‘thin-ness’ limitations and pitch of the features from mandrel formation limitations.
It is now combined with additional techniques such as self-aligned double patterning or DSA (directed self-assembly) to achieve the required CD. These methods can become costly and add several steps to the process. Advanced extreme ultra violet (EUV) lithography should be able to alleviate some of these issues once available but the constant drive to smaller CD will remain a challenge for the future technologies to come.
There is a need to fabricate structures with a CD in the range lower than those obtained using current photolithography techniques. More specifically, there is a need to: (1) get the CD of structures below 10 nm without using EUV lithography; (2) minimize the setup time of the integration steps to increase effective throughput, (3) minimize the number of tools needed to complete the process, and/or (4) reduce the cost of ownership.